2nd/10_Wiki/Topics/Computer_Science_and_Theory/Hardware-Verification.md

id, title, category, status, canonical_id, aliases, duplicate_of, source_trust_level, confidence_score, verification_status, tags, raw_sources, last_reinforced, github_commit, tech_stack

id	title	category	status	canonical_id	aliases	duplicate_of	source_trust_level	confidence_score	verification_status	tags	raw_sources	last_reinforced	github_commit	tech_stack
wiki-2026-0508-hardware-verification	Hardware Verification	10_Wiki/Topics	verified	self	Formal Verification Chip Verification RTL Verification	none	A	0.93	applied	hardware verification formal-methods eda rtl		2026-05-10	pending	language framework SystemVerilog UVM/JasperGold/SymbiYosys

Hardware Verification

매 한 줄

"매 silicon 의 mistake 의 cost ≫ software bug — 매 60-70% chip dev effort 가 verification". Pentium FDIV (1994, $475M recall) 매 watershed; modern flow 매 simulation (UVM) + formal (property checking) + emulation (Palladium/Veloce) + post-silicon validation. 매 RISC-V 의 open verification revolution (2024-26).

매 핵심

매 layers

• Simulation (UVM/SystemVerilog): constrained-random + coverage-driven.
• Formal verification: mathematical proof of property (CDC, register, security).
• Emulation: FPGA/dedicated boxes (Palladium, Veloce, ZeBu) — 매 1000× faster than sim, full SoC.
• Static: linting, CDC (clock domain crossing), RDC (reset domain).
• Post-silicon: bringup on actual die — bugs that escaped pre-si.

매 metrics

• Code coverage: line/branch/toggle/FSM (necessary, not sufficient).
• Functional coverage: covergroups on intent.
• Bug curve: bugs/week vs time — closure when asymptote.

매 응용

1. CPU verification (RISC-V cores, ARM, x86).
2. AI accelerator verification (TPU, GPU, NPU).
3. Safety-critical (ISO 26262 ASIL-D, DO-254).
4. Security (Spectre/Meltdown class — formal info-flow).
5. Cryptography hardware (AES, post-quantum).

💻 패턴

UVM testbench skeleton

class my_test extends uvm_test;
  `uvm_component_utils(my_test)
  my_env env;
  function void build_phase(uvm_phase phase);
    env = my_env::type_id::create("env", this);
  endfunction
  task run_phase(uvm_phase phase);
    my_seq seq = my_seq::type_id::create("seq");
    phase.raise_objection(this);
    seq.start(env.agt.sqr);
    phase.drop_objection(this);
  endtask
endclass

SystemVerilog Assertion (SVA)

property req_ack;
  @(posedge clk) disable iff (rst)
  req |-> ##[1:5] ack;
endproperty
assert property (req_ack) else $error("ack timeout");
cover  property (req_ack);

Formal property (Jasper / SymbiYosys)

// Prove: FIFO never overflows
property no_overflow;
  @(posedge clk) (count == DEPTH) |-> !push;
endproperty
assert property (no_overflow);

Constrained random

class transaction;
  rand bit [31:0] addr;
  rand bit [31:0] data;
  constraint c_align { addr[1:0] == 0; }
  constraint c_range { addr inside {[32'h1000:32'h2000]}; }
endclass

Coverage closure

covergroup cg @(posedge clk);
  cp_addr: coverpoint addr {
    bins low  = {[0:32'h0FFF]};
    bins mid  = {[32'h1000:32'hEFFF]};
    bins high = {[32'hF000:$]};
  }
  cp_kind: coverpoint kind { bins all[] = {READ, WRITE, ATOMIC}; }
  cross cp_addr, cp_kind;
endgroup

Open-source flow (SymbiYosys + Yosys)

# .sby file
[options]
mode prove
depth 20
[engines]
smtbmc z3
[script]
read -formal design.sv
prep -top top
[files]
design.sv
sby -f design.sby

CDC check (Spyglass-style)

read_verilog design.sv
set_top top
analyze cdc
report cdc -severity error

매 결정 기준

상황	Approach
Control logic correctness	Formal (full proof)
Datapath / large bugs	UVM constrained-random
Full SoC software boot	Emulation
Post-RTL freeze	Gate-level sim + FV
Security properties	Formal info-flow (Coq/Sail)
Performance	Hybrid emulation + RTL profiling

기본값: UVM for blocks + formal for control + emulation for system.

🔗 Graph

• 부모: Formal-Methods
• 변형: Formal-Verification
• Adjacent: Model-Checking · Theorem-Proving

🤖 LLM 활용

언제: SVA generation from spec text, UVM boilerplate scaffold, coverage closure analysis, debugging waveform descriptions. 언제 X: signing off tapeout (need human + tool sign-off), safety-critical sole reviewer, novel formal proofs (need expert).

❌ 안티패턴

• Coverage = correctness: 100% code coverage 매 buggy chips ship 의 still.
• No assertions: bugs only at testbench checker → late detection.
• Re-running same seed: random ineffective without seed sweep.
• Skipping CDC: silicon metastability bugs 매 hardest to debug.
• Late formal: starting formal at end of project — embed early on critical blocks.
• No regression triage: failing tests left "to investigate" rot.

🧪 검증 / 중복

• Verified (Accellera UVM 1.2/2020 LRM, Cadence/Synopsys/Siemens EDA whitepapers, Pentium FDIV postmortem, RISC-V International verification WG 2024-25).
• 신뢰도 A.

🕓 Changelog

날짜	변경
2026-05-08	Phase 1
2026-05-10	Manual cleanup — UVM/SVA/formal/CDC patterns